The Design and Implementation of an Open-Source Hardware Trojan for a 64-bit RISC-V CPU

Athanasios Moschos; Angelos D. Keromytis
Poster Section - IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2022

Hardware Trojan (HT) paradigms on modern, realistic and complex designs are scarce. Development of corresponding open-source HT-testbeds is important for research conducted on defense mechanisms and detection methods for HT.

The silicon itself can enable attacks that disable or selectively by-pass fundamental security mechanisms (e.g., memory protection) of modern Central Processing Units (CPUs)

Overwriting data inside the kernel address space from a user process violates address space isolation, a powerful Operating System security mechanism.

Current HT detection methods pertain a prohibitive economic cost, are very time consuming and can lead to the destruction of the Device Under Test